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CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Features
Functional Description
The CY7C1059DV33[1] is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input or output pins (IO0 through IO7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW, and WE LOW). The CY7C1059DV33 is available in 36-ball FBGA and 44-pin TSOP II packages with center power and ground (revolutionary) pinout.
High speed tAA = 10 ns Low active power ICC = 110 mA at 10 ns Low CMOS standby power ISB2 = 20 mA 2.0V data retention Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 44-pin TSOP II package

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE WE OE
INPUT BUFFER ROW DECODER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
1M x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
Note 1. For guidelines about SRAM system design, refer to the Cypress application note AN1064, SRAM System Guidelines available at www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-00061 Rev. *C
*
198 Champion Court
A11 A12 A13 A14 A15 A16 A17 A18 A19
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 26, 2007
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CY7C1059DV33
Pin Configuration
Figure 1. Pin Diagram - 44-Pin TSOP II Top View
NC NC A0 A1 A2 A3 A4 CE IO0 IO1 VCC VSS IO2 IO3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE IO 7 IO 6 VSS VCC IO 5 IO 4 A14 A13 A12 A11 A10 A19 NC NC
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 110 20 -12 12 100 20 Unit ns mA mA
Document #: 001-00061 Rev. *C
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CY7C1059DV33
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC to Relative GND[2] .....-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] .................................... -0.3V to VCC + 0.3V
DC Input Voltage[2] ................................ -0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current --TTL Inputs Automatic CE Power Down Current --CMOS Inputs Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 110 40 20 2.0 -0.3 -1 -1 Max Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 100 35 20 -12 Max Unit V V V V A A mA mA mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.] Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 12 12 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board TSOP II 51.43 15.8 Unit C/W C/W
Notes 2. VIL(min) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00061 Rev. *C
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CY7C1059DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c). Figure 2. AC Test Loads and Waveforms
Z = 50 OUTPUT 50
* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT
3.0V 90% 30 pF* GND 10%
ALL INPUT PULSES 90% 10%
1.5V (a) Rise Time: 1 V/ns R 317 (b) Fall Time: 1 V/ns
High-Z characteristics: 3.3V OUTPUT 5 pF (c)
R2 351
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR[3] tR[5] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Conditions[4] Min 2.0 20 0 tRC Max Unit V mA ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Notes 4. No inputs may exceed VCC + 0.3V. 5. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document #: 001-00061 Rev. *C
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CY7C1059DV33
AC Switching Characteristics
Over the Operating Range[6] Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE LOW to High-Z[8, 9] 3 5 0 10 10 7 7 0 0 7 5 0 3 5 12 8 8 0 0 8 6 0 3 6 0 12 Low-Z[9] 0 5 3 6 2.5 10 5 0 6 100 10 10 2.5 12 6 100 12 12 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -10 Min Max Min -12 Max Unit
CE HIGH to High-Z[8, 9] CE LOW to Power up CE HIGH to Power down
[10, 11]
Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z[9] WE LOW to High-Z[8, 9]
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER is the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of "AC Test Loads and Waveforms" on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-00061 Rev. *C
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CY7C1059DV33
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Figure 3. Read Cycle No. 1[12, 13]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
Figure 4. Read Cycle No. 2[13, 14]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid before or coincident with CE transition LOW.
Document #: 001-00061 Rev. *C
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CY7C1059DV33
Switching Waveforms(continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)
Figure 5. Write Cycle No. 1[15, 16]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (WE Controlled, OE LOW)
Figure 6. Write Cycle No. 2[16]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 17 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Notes 15. Data IO is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. During this period the IOs are in the output state and input signals must not be applied.
Document #: 001-00061 Rev. *C
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CY7C1059DV33
Truth Table
CE H L L L OE X L X H WE X H L H IO0-IO7 High-Z Data Out Data In High-Z Mode Power Down Read Write Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 12 Ordering Code CY7C1059DV33-10ZSXI CY7C1059DV33-12ZSXI Package Diagram 51-85087 51-85087 Package Type 44-pin TSOP II (Pb-Free) 44-pin TSOP II (Pb-Free) Operating Range Industrial
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 7. 44-Pin TSOP II (51-85087)
51-85087-*A
Document #: 001-00061 Rev. *C
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CY7C1059DV33
Document History Page
Document Title: CY7C1059DV33, 8-Mbit (1M x 8) Static RAM Document Number: 001-00061 REV. ** *A ECN NO. Issue Date 342195 380574 See ECN See ECN Orig. of Change PCI SYT New Data Sheet Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10 and 12 ns speed bins respectively ICC (Ind'l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10 and 12 ns speed bins respectively Changed the Capacitance values from 8 pF to 10 pF on Page # 3 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed -8 and -12 Speed bins from product offering, Removed Commercial Operating Range option, Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Updated footnote #7 on High-Z parameter measurement Added footnote #11 Changed the Description of IIX from Input Load Current to Input Leakage Current. Updated the Ordering Information table and Replaced Package Name column with Package Diagram. Description of Change
*B
485796
See ECN
NXR
*C
1513285
See ECN
VKN/AESA Converted from preliminary to final Added 12 ns speed bin Changed CIN and COUT specs from 16 pF to 12 pF Changed tOHA spec from 3 ns to 2.5 ns Updated Ordering information table
(c) Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-00061 Rev. *C
Revised September 26, 2007
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